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Ixiasoft
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
You must specify the logical library names of Quartus® Prime simulation libraries to the vsim command, as Finding Logical Library Names in Simulation Library Compiler Output.
You can additionally choose the simulator specific options to elaborate the top-level testbench module as you wish. However, there are some specific elaboration options required to simulate some of the Intel® FPGA IP.
The .vo and .vho netlist files generated by the Quartus® Prime software generally do not require specific compilation options.