Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

3.5.3. Example my_sim.tcl Simulation Script

The following example simulation script compiles, elaborates, and simulates the testbench, as Example Using msim_setup.tcl without Customization describes.

# this script must be in the same directory as msim_setup.tcl

# create work library
vlib work

# compile design and testbench files into work library
vlog -sv my_design.sv tb.sv

# source the file to define the commands such as com and 
# elab_debug, and to call file_copy to copy any IP memory files
# (such as .hex and .mif files) to this directory.
source ./msim_setup.tcl

# compile quartus simulation libraries. This command will not do 
# anything when called by Questa Intel FPGA Edition, since we use 
# precompiled quartus simulation libraries.
dev_com

# compile IP RTL files
com

# toplevel module name to be simulated. This is the top-level 
# testbench module
set TOP_LEVEL_NAME “tb”

# call elaboration command. 
elab_debug

# add waveforms
add wave -r /*

# run simulation
run -all

# exit simulation
quit