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2.1. FPGA Simulation Essential Elements
2.2. Overview of Simulation Tool Flow
2.3. Simulation Tool Flow
2.4. Supported Hardware Description Languages
2.5. Supported Simulation Types
2.6. Supported Simulators
2.7. Post-Fit Simulation Support by FPGA Family
2.8. Automating Simulation with the Run Simulation Feature
2.9. Intel FPGA Simulation Basics Revision History
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
Optional Setting To Run Simulation for Specific Time Interval
Optional Setting for Custom Wave File
Optional Setting for Elaboration Options
Simulator GUI or Batch Mode Operation Optional Setting
2.8.2.3. Launching Simulation with the Run Simulation Feature
2.8.2.4. Running RTL Simulation using Run Simulation
2.8.2.5. Output Directories and Files for Run Simulation
3.1. Types of Questa* Intel® FPGA Edition Commands
3.2. Commands to Invoke Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
3.6. Using the Qrun Flow
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation
3.8.2. Files Required for Gate-Level Simulation
3.8.3. Step 1: Generate Gate-Level Netlists for Simulation
3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
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2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
There are both required and optional setting for use of Run Simulation in batch mode.
The following examples show how to specify optional simulation settings for use of Run Simulation in batch mode:
Optional Setting To Run Simulation for Specific Time Interval
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR “1 ns” \ -section_id testbenchSet
Optional Setting for Custom Wave File
set_global_assignment -name EDA_SIMULATION_WAVE_FILE_QUESTA_INTEL wave.do \ -section_id testbenchSet
Optional Setting for Elaboration Options
For Questa* Intel® FPGA Edition or QuestaSim*:
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "questa=-suppress 2732 -suppress 14408 -suppress 16154" -section_id eda_simulation
For VCS* (Linux-only):
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "vcs=+define+IP7521SERDES_UX_SIMSPEED\ " -section_id eda_simulation
For VCS* MX (Linux-only):
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "vcsmx=+define+IP7521SERDES_UX_SIMSPEED\ " -section_id eda_simulation
For Active-HDL* (Windows* only):
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "activehdl=<third-party elab options>" -section_id eda_simulation
For Riviera-PRO*:
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "rivierapro=<third-party elab option(s)>" -section_id eda_simulation
For Xcelium* (Linux-only):
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "xcelium=<third-party elab option(s)>" -section_id eda_simulation
Simulator GUI or Batch Mode Operation Optional Setting
The default mode of this option is GUI mode. For simulator batch mode:
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL ON -section_id eda_simulation