Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

2.8.2.5. Output Directories and Files for Run Simulation

Run Simulation generates subdirectories and files inside the following output directories, according to your specifications in the Simulation Options.

./simulation/<simulator/arbitrary>/rtlsim/
   <project>_run_msim_rtl_<hdl>.do		
      A .do file containing the simulator settings
   run_sim_command.sh (or .bat for Windows)
      A .sh/.bat file to rerun the simulation only (standalone, i.e., without 
      rerunning Quartus Prime compilation and elaboration)
   <simulator/arbitrary>_transcript.log
	  A simulator transcript file
./simulation/<simulator or arbitrary>/rtlsim/<project>_iputf_input
   ./aldec
      rivierapro_setup.tcl
   ./common
      modelsim_files.tcl
      riviera_files.tcl
      vcs_files.tcl
      vcsmx_files.tcl
      xcelium_files.tcl
   ./mentor
      msim_setup.tcl
   ./synopsys
      ./vcs
         vcs_setup.sh
      ./vcsmx
         synopsys_sim.setup
         vcsmx_setup.sh
   ./xcelium
      cds.lib
      hdl.var
      xcelium_setup.sh
      ./cds_libs
         Project library files