Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems

Note: If you intend to simulate an Intel FPGA IP example design generated by Platform Designer, be aware that the example design also includes a testbench to simulate the example design, and a top-level simulation script that you can run to execute all the commands to perform compilation, elaboration, and simulation. Refer to the IP user guide or the IP Example Design user guide to generate the example design files for simulation including a top-level simulation script.

The following describes simulation of an RTL design that includes IP variants (.ip files) or Platform Designer systems (.qsys files).

Files Required for RTL Simulation

  • Your HDL design files, Platform Designer generated IP RTL files, and testbench files.
    Note: Questa* Intel® FPGA Edition does not require the Quartus® Prime simulation library files because these files are precompiled and included in Questa* Intel® FPGA Edition. Rather, use only the precompiled libraries that Questa* Intel® FPGA Edition includes, as Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries describes.

As with any simulation, the RTL simulation flow consists of running simulator specific commands in three stages: compilation, elaboration, and simulation. You can place the compilation commands in one Tcl script, and the elaboration and simulation commands in another Tcl script.