Visible to Intel only — GUID: pmv1671479252040
Ixiasoft
2.1. FPGA Simulation Essential Elements
2.2. Overview of Simulation Tool Flow
2.3. Simulation Tool Flow
2.4. Supported Hardware Description Languages
2.5. Supported Simulation Types
2.6. Supported Simulators
2.7. Post-Fit Simulation Support by FPGA Family
2.8. Automating Simulation with the Run Simulation Feature
2.9. Intel FPGA Simulation Basics Revision History
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
2.8.2.3. Launching Simulation with the Run Simulation Feature
2.8.2.4. Running RTL Simulation using Run Simulation
2.8.2.5. Output Directories and Files for Run Simulation
3.1. Types of Questa* Intel® FPGA Edition Commands
3.2. Commands to Invoke Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
3.6. Using the Qrun Flow
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation
3.8.2. Files Required for Gate-Level Simulation
3.8.3. Step 1: Generate Gate-Level Netlists for Simulation
3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
Visible to Intel only — GUID: pmv1671479252040
Ixiasoft
3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems
Note: If you intend to simulate an Intel FPGA IP example design generated by Platform Designer, be aware that the example design also includes a testbench to simulate the example design, and a top-level simulation script that you can run to execute all the commands to perform compilation, elaboration, and simulation. Refer to the IP user guide or the IP Example Design user guide to generate the example design files for simulation including a top-level simulation script.
The following describes simulation of an RTL design that includes IP variants (.ip files) or Platform Designer systems (.qsys files).
Files Required for RTL Simulation
- Your HDL design files, Platform Designer generated IP RTL files, and testbench files.
Note: Questa* Intel® FPGA Edition does not require the Quartus® Prime simulation library files because these files are precompiled and included in Questa* Intel® FPGA Edition. Rather, use only the precompiled libraries that Questa* Intel® FPGA Edition includes, as Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries describes.
As with any simulation, the RTL simulation flow consists of running simulator specific commands in three stages: compilation, elaboration, and simulation. You can place the compilation commands in one Tcl script, and the elaboration and simulation commands in another Tcl script.