Questa* Intel® FPGA Edition Simulation User Guide

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ID 730191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to the Questa* Intel® FPGA Edition Simulator 2. FPGA Simulation Basics 3. Simulating with Questa* Intel® FPGA Edition 4. Revision History for Questa Intel FPGA Edition Simulation User Guide A. Quartus® Prime Pro Edition User Guides
1. Introduction to the Questa* Intel® FPGA Edition Simulator x
1.1. Simulator Versions and Licensing 1.2. Accessing Siemens EDA-Provided Simulator Documentation 1.3. Document Prerequisites
1.1. Simulator Versions and Licensing x
1.1.1. Comparing Simulator Versions 1.1.2. Post-Fit Simulation Support by FPGA Family
2. FPGA Simulation Basics x
2.1. FPGA Simulation Essential Elements 2.2. Overview of Simulation Tool Flow 2.3. Simulation Tool Flow 2.4. Supported Hardware Description Languages 2.5. Supported Simulation Types 2.6. Supported Simulators 2.7. Post-Fit Simulation Support by FPGA Family 2.8. Automating Simulation with the Run Simulation Feature 2.9. Intel FPGA Simulation Basics Revision History
2.2. Overview of Simulation Tool Flow x
2.2.1. Compilation Stage 2.2.2. Elaboration Stage 2.2.3. Simulation Stage
2.3. Simulation Tool Flow x
2.3.1. Specifying Logical Libraries 2.3.2. Compiling Files Into Library Directories 2.3.3. The Quartus® Prime Simulation Library 2.3.4. Understanding Elaboration 2.3.5. Commands To Configure and Run Simulation 2.3.6. FPGA Simulation Generic Workflow
2.3.1. Specifying Logical Libraries x
2.3.1.1. Why Do We Need Logical Library Names?
2.3.2. Compiling Files Into Library Directories x
2.3.2.1. Inputs to Compilation Commands 2.3.2.2. Order of Files for Compilation Commands 2.3.2.3. Compilation Command Line Options 2.3.2.4. Module Definitions in Library Directories
2.3.3. The Quartus® Prime Simulation Library x
2.3.3.1. The Quartus® Prime Simulation Library Compiler 2.3.3.2. Running the Simulation Library Compiler in a Terminal 2.3.3.3. Running the Simulation Library Compiler in the GUI 2.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
2.3.4. Understanding Elaboration x
2.3.4.1. Elaboration Binding Phase 2.3.4.2. Elaboration Checks 2.3.4.3. Elaboration Options
2.8. Automating Simulation with the Run Simulation Feature x
2.8.1. Setting Up the Run Simulation Feature 2.8.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line)
2.8.1. Setting Up the Run Simulation Feature x
2.8.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 2.8.1.2. Simulation Options (Board and IP Settings Page) 2.8.1.3. Simulation Flow Settings (EDA Tool Settings Page) 2.8.1.4. More EDA Netlist Writer Settings (EDA Tool Settings Page)
2.8.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
2.8.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 2.8.2.2. Optional Simulation Settings for Run Simulation (Batch Mode) 2.8.2.3. Launching Simulation with the Run Simulation Feature 2.8.2.4. Running RTL Simulation using Run Simulation 2.8.2.5. Output Directories and Files for Run Simulation
3. Simulating with Questa* Intel® FPGA Edition x
3.1. Types of Questa* Intel® FPGA Edition Commands 3.2. Commands to Invoke Questa* Intel® FPGA Edition 3.3. Commands to Compile, Elaborate, and Simulate 3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries 3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation 3.6. Using the Qrun Flow 3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition 3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate x
3.3.1. Compilation Command Examples 3.3.2. Finding Logical Library Names in Simulation Library Compiler Output 3.3.3. Elaboration Command Examples 3.3.4. Simulation Command Examples 3.3.5. Complete Tcl Script Example
3.3.1. Compilation Command Examples x
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library 3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work) 3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo 3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1 3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg 3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.3. Elaboration Command Examples x
3.3.3.1. Elaboration Example 1: Elaborate the Test Top-level Testbench Module 3.3.3.2. Elaboration Example 2: Elaborate the Test Top-level Testbench Module and Preserve All Signals 3.3.3.3. Elaboration Example 3: Elaborate Top-Level Testbench Module my_test
3.3.4. Simulation Command Examples x
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench 3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy 3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation x
3.5.1. Commands Defined in msim_setup.tcl 3.5.2. Example Using msim_setup.tcl without Customization 3.5.3. Example my_sim.tcl Simulation Script 3.5.4. Passing In Custom Compilation and Elaboration Options for msim_setup.tcl 3.5.5. Finding All Custom Variables
3.6. Using the Qrun Flow x
3.6.1. Specifying Simulation File Generation Settings 3.6.2. Generating the Simulation Model and Setup Scripts 3.6.3. Generating the Testbench System 3.6.4. Generating Example Design Simulation Files
3.7. Performing RTL Simulation with Questa* Intel® FPGA Edition x
3.7.1. Simulating an RTL Design without IP Variants or Platform Designer Systems 3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems
3.7.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems x
3.7.2.1. Compilation Stage - Simulation with IP 3.7.2.2. Elaboration Stage - Simulation with IP 3.7.2.3. Simulation Stage - Simulation with IP
3.7.2.1. Compilation Stage - Simulation with IP x
3.7.2.1.1. Customizing the Generated Simulation Script
3.8. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition x
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation 3.8.2. Files Required for Gate-Level Simulation 3.8.3. Step 1: Generate Gate-Level Netlists for Simulation 3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation 3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation 3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
4. Revision History for Questa Intel FPGA Edition Simulation User Guide x
4.1. Questa Intel FPGA Edition Simulation User Guide Archive
Answers to Top FAQs
1. Introduction to the Questa* Intel® FPGA Edition Simulator
2. FPGA Simulation Basics
3. Simulating with Questa* Intel® FPGA Edition
4. Revision History for Questa Intel FPGA Edition Simulation User Guide
A. Quartus® Prime Pro Edition User Guides

3.8.3. Step 1: Generate Gate-Level Netlists for Simulation

The Quartus® Prime EDA Netlist Writer (quartus_eda on the command line) allows you to write gate-level (technology mapped) netlists for simulation and other applications.12

The EDA netlist writer can generate a Verilog Netlist (.vo file) or a VHDL Netlist (.vho file) for the following types of design ports:

  • Single-bit signal types
  • One-dimensional arrays
  • Two-dimensional arrays

The EDA Netlist Writer does not support complex data types, such as enums, stucts, unions, or interfaces, at the external boundary of the design or the design partition.

To the run the EDA Netlist Writer GUI to generate a gate-level netlist for simulation:

  1. In the Quartus® Prime software, click Assignments > Settings > EDA Tool Settings to specify generation options for the Questa* Intel® FPGA Edition simulator.
    Figure 16. Specifying EDA Netlist Writer Settings for Questa* Intel® FPGA Edition


  2. To compile your design to the desired stage, perform one of the following:
    • To generate the post-synthesis netlist for simulation, double-click Analysis & Synthesis on the Compilation Dashboard
    • To generate the post-fit netlist for simulation, double-click Fitter on the Compilation Dashboard.
    Figure 17. Compiler Stages in Compilation Dashboard


  3. To start EDA Netlist Writer, click EDA Netlist Writer on the Compilation Dashboard. The EDA Netlist Writer generates the netlist, according to your specifications from step 1.
    Figure 18. EDA Netlist Writer Command in Compilation Dashboard


Alternatively, you can start the EDA Netlist Writer by running the quartus_eda command in a shell, with a set of command-line options that specify the type of netlist to produce. To view all the command line options related to simulation, run quartus_eda –-help=simulation.

Table 18.   quartus_eda Command Options
quartus_eda Options Option Description
--simulation

Specifies generation of a Verilog (.vo) or VHDL (.vho) gate-level simulation netlist.13

--tool Specifies the supported simulator that reads the netlist. Supported options are:
  • modelsim, questa_oem, vcs, vcs_mx, xcelium, rivierapro, activehdl, verilogxl.
--format Specifies the supported language format of the simulation output gate-level netlist. Supported options are verilog or vhdl.
--resynthesis Specifies that quartus_eda creates a Verilog Quartus Map (.vqm) netlist. The software can resynthesize the netlist as an RTL input, from the gate-level netlist. Only use this option with partitions containing core logic only, not periphery. The sub-option is a flag only and takes no arguments.
--partition Specifies an individual partition by name for netlist output. For no partition argument, the entire design writes out to a single file. The partition argument takes the name of a partition in the design. You can use the --partition option with the --simulation (.vo, .vho) and --resynthesis (.vqm) output.
--exclude_sub_partitions

Flag that limits the output to the netlist for the partition you specify. This flag is only valid with the --partition option. The software instantiates subpartitions as module instances in the netlist. The sub-option is a flag only and takes no arguments.

You can specify the root_partition as the partition name in the --partition option to get the top level partition, which is useful when using the --exclude_sub_partitions flag.

--module_name

Renames a partition in the output netlist file. By default, the software uses the partition name as the module name in the netlist file. This option is only valid when you use the --partition option. You can rename any module using --module_name=abc=xyz.

The output netlist file name format is: <revision>.<partition name>.<vo or vho>. By default, the Quartus® Prime software writes the netlist file to the simulation directory (for example, simulation/questa), unless you specify an output_directory (using a command line option or .qsf assignment).

Related Information
12 Gate-level simulation can be slower and harder to debug for larger designs and therefore may not be suitable as the primary means of validation.
13 This option overrides any Quartus® Prime Settings File (.qsf) setting.
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