Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

3.6.3. Generating the Testbench System

You can optionally generate a testbench system that instantiates the original system, adding bus functional models to drive the top-level interfaces. Once generated, the bus functional models can interact with the system or IP in the simulator.

Platform Designer generates the simulation model and setup scripts according to your specifications in Specifying Simulation File Generation Settings.

To generate the testbench system for a Platform Designer system or IP component, follow these steps:
  1. In the Quartus® Prime Pro Edition software, click Tools > Platform Designer and open or create an IP variant or Platform Designer system.
  2. After specifying any IP component or system parameters in the parameter editor, click the Generate > Generate Testbench System button. The Generation dialog box appears.
  3. Under Testbench System, select either Verilog or VHDL for Create testbench simulation model. Selecting one of these options makes the Modelsim flow selection setting editable.
  4. For Modelsim flow selection, make sure Qrun is selected to enable the Qrun flow. The alternative setting runs the Traditional flow.
    Figure 13. Generation Dialog Box Settings


  5. Click Generate. Platform Designer generates the simulation models and setup scripts for your system or IP component under the specified Output Directory.