Questa* Intel® FPGA Edition Simulation User Guide

ID 730191
Date 4/01/2024
Public
Document Table of Contents

2.3.6. FPGA Simulation Generic Workflow

The following describes the high level workflow for simulation of any Quartus® Prime design using any supported simulator:

Figure 6. Generic FPGA Simulation Workflow


  1. Identify all of the HDL simulation files, including design files, simulation library files, and HDL testbench files.
  2. Identify the top-level test bench module for simulation.
  3. For each HDL simulation file, determine the logical library for compilation, and any compilation options for compiling the file.6
  4. Determine any simulator-specific elaboration options required for elaborating the top- level testbench module, as Understanding Elaboration describes.
  5. Use the information gathered in previous steps to assemble a simulation script to compile, elaborate, and simulate the design. This script must include commands to perform the following:

The Quartus® Prime software can generate simulator-specific simulation scripts to automate some of the simulation processing in your preferred simulation environment.

The Quartus® Prime software can generate a simulator specific simulation script for an IP core, or a Platform Designer system, for use in RTL simulation. The script includes commands to compile all the IP RTL files, as well as an elaboration command with any simulator specific options.

The Quartus® Prime software can generate a simulation library compilation script for a given simulator, device family, and language. This script includes commands to compile the simulation library files for the specified simulator, device family, and language. You can use this script for RTL simulation and gate-level simulation.

6 In general, you can compile most HDL simulation files into the default work library.