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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode
The PLL is operational after it achieves lock in user mode. Before transferring data using SERDES block with the LVDS SERDES IP, ensure that the PLL is locked to the reference clock.
Altera recommends that you follow these steps to initialize the LVDS SERDES IP in non-DPA mode:
- During entry into user mode, assert the pll_areset signal for at least 10 ns.
You can also perform this step at any time in user mode operation to reset the interface.
- After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
In the external PLL mode, you may observe a delay between the assertion of the ext_pll_locked and pll_locked signals. The ext_pll_locked signal asserts when the external PLL locks while the pll_locked signal asserts after the external PLL and CPA lock. Always use the pll_locked signal to determine if the SERDES block is ready for operation.
After the PLL lock port from the LVDS SERDES IP asserts and becomes stable, the SERDES blocks are ready for operation.
After the initialization, you can proceed to align the word boundaries (bit slip).