Visible to Intel only — GUID: sam1403482511865
Ixiasoft
Visible to Intel only — GUID: sam1403482511865
Ixiasoft
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP
From the IOPLL IP | To the LVDS SERDES IP Transmitter or Receiver |
---|---|
lvds_clk[1:0] (serial clock output signal)
The serial clock output can only drive ext_lvds_clk[1:0] on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic. |
ext_lvds_clk[1:0] (serial clock input to the transmitter or receiver) |
loaden[1:0] (load enable output)
|
ext_loaden[1:0] (load enable to the transmitter or receiver) |
outclk4 (parallel clock output) |
ext_coreclock (core clock to the LVDS SERDES Intel FPGA IP) |
locked |
ext_pll_locked This signal indicates when external PLL is locked. It does not indicate if SERDES is ready for initialization. |
reset |
pll_areset (asynchronous PLL reset port) |
phout[7:0]
|
ext_vcoph[7:0] This signal is required for all transmitter or receiver modes. |