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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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6.1.1.1. Obtaining RSKM Report
For LVDS SERDES receivers, the Quartus® Prime software generates the RSKM report (report_rskm) that provides the SW, TUI or clock cycle, and RSKM values for the non-DPA mode.
Before you begin, compile your project and ensure that the compilation is successful.
- From the Quartus® Prime menu, select Tools > Timing Analyzer.
The Timing Analyzer window appears.
- In the Task pane of the Timing Analyzer window, double-click Update Timing Netlist.
- From the Timing Analyzer menu, select Reports > IP Specific > Report RSKM.