Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series

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ID 721819
Date 9/05/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview 2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture 3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter 4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver 5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide 6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines 9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series 11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture x
2.1. F-Series and I-Series GPIO Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Differential I/O Bit Position 3.4. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations
3.4. Clocking the Differential Transmitters x
3.4.1. Transmitter Output Clock Parameters Settings
3.4.1. Transmitter Output Clock Parameters Settings x
3.4.1.1. Edge-Aligned tx_outclock to tx_out 3.4.1.2. Center-Aligned tx_outclock to tx_out
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Generating the LVDS SERDES Intel® FPGA IP 5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.6. LVDS SERDES Intel® FPGA IP Signals
5.1.4. Generating the LVDS SERDES Intel® FPGA IP x
5.1.4.1. Intel® FPGA IP Generation Output
5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.5.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.5.2. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.5.3. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.5.4. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.5.5. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO Bank
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series

9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines

These debug guidelines are initial debug actions and do not necessarily resolve the failures in your designs.
Table 37.  LVDS SERDES I/O Debug GuidelinesThis table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing LVDS SERDES systems with F-Series and I-Series devices.
Failure Symptoms Recommended Debug Actions

pll_locked signal is unable to assert

  • Ensure that the pll_areset signal is deasserted.
  • If you are using the LVDS SERDES IP with the external PLL mode, ensure that the desired PLL IP settings match the recommended settings from the LVDS SERDES IP Clock Resource Summary tab.
    Note: Use simple PLL settings when debugging this failure to limit the failure scope. Ensure that the external PLL automatic switchover and dynamic reconfiguration modes are disabled.
  • Switch to use internal PLL to verify if the same failure occurs when using internal PLL.

rx_dpa_locked signal is unable to assert

  • Ensure that the pll_locked signal is asserted and the rx_dpa_reset is deasserted. It is important to ensure that the PLL is able to lock to confirm that the LVDS SERDES IP input clock frequency is correct.
  • Provide a training pattern to the DPA block with a toggling signal that conforms to the True Differential Signaling input buffer specification.

Random bit error occurs at LVDS SERDES receiver parallel data out bus
  • Ensure that RD termination is applied. You can enable OCT RD using the assignment editor in the Quartus® Prime software or place an on-board 100 Ω resistor termination. Refer to the related information.
  • Measure the rx_in_p and rx_in_n signal voltages and ensure that the voltages conforms to the VID and VICM requirements.
  • If the rx_in_p and rx_in_n signals have jitter, ensure that the signals have sufficient data valid window that conforms to the sampling window requirements.
  • Re-initialize the LVDS SERDES receiver reset sequence and ensure that:
    • The pll_locked signal is asserted.
    • The rx_dpa_locked signal is asserted.
    • The rx_fifo_reset signal is deasserted after FIFO reset (for DPA FIFO mode only).
    • The rx_divfwdclk (soft-CDR mode only) and rx_coreclock signals have the correct clock frequencies ( ).

LVDS SERDES receiver parallel data out is not matching a training pattern

Assert the rx_bitslip_ctrl signal for one clock cycle to add bit latency to the received bitstream. Continue to assert the signal until you see the expected pattern at the rx_out bus.

The rx_bitslip_max signal asserts before it reaches the bit slip rollover value

  • Check the bit slip rollover value in the LVDS SERDES IP. Set the rollover value based on .
  • Assert the rx_bitslip_reset signal before starting the bit slip and the reset must hold for at least one parallel clock cycle (based on rx_coreclock or rx_divfwdck).
Related Information
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