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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
Document Version | Quartus® Prime Version | Changes |
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2024.09.05 | 24.2 |
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2023.12.11 | 23.4 |
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2023.04.10 | 23.1 |
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2022.11.30 | 22.1 |
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2022.06.09 | 22.1 | Updated the topic about placing LVDS transmitters and receivers in the same GPIO bank to add related information links to information about true differential signaling I/O standard specifications and termination. |
2022.03.28 | 22.1 |
Note: For the history of previous revisions and to access previous versions of this user guide, refer to the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide.
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