Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 9/05/2024
Public
Document Table of Contents

11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series

Document Version Quartus® Prime Version Changes
2024.09.05 24.2
  • Corrected the LVDS SERDES Intel® FPGA IP version to 20.0.1.
  • Removed Enable DPA loss of lock on one change and Enable DPA alignment only to rising edges of data from the table Receiver Settings Tab—DPA Settings.
  • Removed the mention about Enable DPA loss of lock on one change from the topic Initializing the LVDS SERDES IP in DPA Mode.
  • Updated product family name to " Agilex™ 7".
2023.12.11 23.4
  • Changed the term "high-speed SERDES" to "LVDS SERDES".
  • Updated the figure showing the soft-CDR LVDS receiver interface with the IOPLL IP with LVDS transmitter in the same sub-bank.
2023.04.10 23.1
  • Removed the following sections:
    • Combined LVDS SERDES IP Transmitter and Receiver Design Example
    • LVDS SERDES IP Dynamic Phase Shift Design Example
  • Added a link to Placing LVDS Transmitters and Receivers in the Same GPIO Bank in the LVDS SERDES Intel FPGA IP Signals topic.
  • Updated product family name to " Intel Agilex® 7".
  • Retitled the document from Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide to Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series.
2022.11.30 22.1
  • Updated the VCO Frequency information in Table: Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode)
2022.06.09 22.1

Updated the topic about placing LVDS transmitters and receivers in the same GPIO bank to add related information links to information about true differential signaling I/O standard specifications and termination.

2022.03.28 22.1
  • Initial release.
    • Moved the contents from the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide.
    • Restructured and rewritten the contents to improve ease of reference and modularity.
    • Updated the LVDS SERDES IP receiver settings to include the RCCS parameter.
    • Corrected the figure showing the basic LVDS SERDES IP system with internal PLL. The LVDS SERDES IP for Intel® Agilex™ F-Series and I-Series devices does not support the duplex feature.
    • Updated the guidelines for placing LVDS transmitters and receivers in the same GPIO bank to specify that you can only place 11 DPA or non-DPA receivers. You need one channel in the sub-bank for the I/O PLL reference clock input.
Note: For the history of previous revisions and to access previous versions of this user guide, refer to the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide.