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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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4.2.1.2. Center-Aligned inclock to rx_in
To specify a center-aligned relationship between inclock and rx_in, specify a 180° phase shift.
Figure 17. 180° Center-Aligned inclock ×8 Deserializer Waveform with a Single Rate Clock
The inclock to rx_in phase shift relationship you specify is independent of the inclock frequency.
To specify a center-aligned DDR inclock to rx_in relationship, specify a 180° phase shift.
Figure 18. 180° Center Aligned inclock ×x8 Deserializer Waveform with a DDR Clock