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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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4.1.4. Deserializer
The deserializer includes shift registers and parallel load registers. The deserializer sends a maximum of 10 bits to the internal logic. You can statically set the deserialization factor from ×3 to ×10 in the LVDS SERDES Intel® FPGA IP parameter editor.
The I/O element (IOE) contains two data input registers. Each data input register can operate in double data rate (DDR) or single data rate (SDR) mode. Use the GPIO Intel® FPGA IP to bypass the serializer and operate in DDR and SDR modes.
If you bypass the deserializer, you cannot use the DPA block and data realignment circuit.
Figure 15. Deserializer BypassThis figure shows the deserializer bypass path.
Mode | Description |
---|---|
SDR (×1) |
|
DDR (×2) |
|