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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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3.1. LVDS SERDES Transmitter Blocks
In the F-Series and I-Series LVDS SERDES transmitter, the serializer receives up to 10 bits wide parallel data from the FPGA fabric.
Figure 3. LVDS SERDES Transmitter
- The serializer clocks the data into the load registers and serializes the data using shift registers.
- The I/O PLL that drives the data to the differential buffer clocks the shift registers.
- The shift registers transmit the MSB of the parallel data first.
Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the serializer.