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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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8.3. Pin Placement for Differential Channels
Each F-Series and I-Series GPIO sub-bank contains its own PLL. The PLL can drive all receiver and transmitter channels in the same sub-bank. However, the PLL of the sub-bank cannot drive receiver and transmitter channels in another GPIO sub-bank. You must use the dedicated clock pins to drive the LVDS SERDES PLLs.
Pins Arrangement in the GPIO Bank
In the device pin out files, the following pin index numbers indicate the location of the pins in a single GPIO bank:
- 0 to 47—bottom sub-bank
- 48 to 95—top sub-bank
PLLs Driving DPA-Enabled Differential Receiver Channels
- For differential receivers, the PLL can drive all channels in the same I/O sub-bank but cannot drive across banks.
- Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
- DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.