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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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2.2. SERDES Blocks, Modes, and Clock Domains
Figure 2. SERDES CircuitryThis figure shows a transmitter and receiver block diagram for the SERDES circuitry with the interface signals of the transmitter and receiver data paths. The figure shows a transmitter and a receiver sharing an I/O PLL as they are in the same sub-bank and using the same I/O PLL resource. In single data rate (SDR) and double data rate (DDR) modes, the data widths are 1 and 2 bits, respectively.
Data Path | Mode | Block | Clock Domain |
---|---|---|---|
Transmitter | TX | Serializer | SERDES clock domain |
Receiver | DPA-FIFO | DPA | DPA clock domain |
Synchronizer | DPA-SERDES clock domain crossing | ||
Bit Slip | SERDES clock domain | ||
Deserializer | SERDES clock domain | ||
Non-DPA | DPA | Not used | |
Synchronizer | Not used | ||
Bit Slip | SERDES clock domain | ||
Deserializer | SERDES clock domain | ||
Soft-CDR | DPA | DPA clock domain | |
Bit Slip | DPA clock domain | ||
Deserializer | DPA clock domain |