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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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5.2. LVDS Interface with External PLL Mode
The LVDS SERDES IP parameter editor provides an option to implement the LVDS interface with the Use External PLL option. With this option turned on you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings.
If you enable the Use External PLL option with the LVDS SERDES IP core transmitter and receiver, the following signals are required from the IOPLL Intel® FPGA IP:
- Serial clock (fast clock) input to the SERDES of the LVDS SERDES IP transmitter and receiver
- Load enable to the SERDES of the LVDS SERDES IP transmitter and receiver
- Parallel clock (core clock) used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
- Asynchronous PLL reset port of the LVDS SERDES IP receiver
- PLL VCO signal for the DPA and soft-CDR modes of the LVDS SERDES IP receiver
The Clock Resource Summary tab in the LVDS SERDES IP parameter editor provides the details for the signals in the preceding list.
You must instantiate an IOPLL IP to generate the various clocks and load enable signals. Configure these settings in the IOPLL IP parameter editor:
- In the Settings tab, select Enable LVDS_CLK/LOADEN 0 & 1 for the Access to PLL LVDS_CLK/LOADEN output port parameter.
- In the PLL tab:
- Set the Output Clocks settings.
- Select the Compensation Mode according to the following table.
LVDS Functional Mode | IOPLL IP Compensation Mode |
---|---|
TX, RX DPA, RX Soft-CDR | direct |
RX non-DPA | lvds |