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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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2.1. F-Series and I-Series GPIO Banks, SERDES, and DPA Locations
The GPIO banks are located at the top and bottom I/O bank rows.
Figure 1. GPIO Bank Structure (Die Top View)This figure shows the GPIO bank structure of F-Series and I-Series devices. The figure shows the view of the die as shown in the Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of GPIO banks. Refer to the device pin-out files for available GPIO banks and the locations of the SDM shared and HPS shared GPIO banks for each device package.
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