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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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6.1.3. Timing Analysis for the External PLL Mode
If you enable the Use external PLL parameter in the PLL Settings tab, the IP generation does not create clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.
The Quartus® Prime software derives some of the SERDES constraints from the PLL clocks. Therefore, the Quartus® Prime software must generate the external PLL clock settings before the LVDS SERDES IP clock settings. In the .qsf of your project, ensure that the line for the .ip file of the IOPLL IP appears before the line for the .ip file of the LVDS SERDES IP.