Visible to Intel only — GUID: pro1551324804850
Ixiasoft
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
Visible to Intel only — GUID: pro1551324804850
Ixiasoft
8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO Bank
If you want to place both LVDS SERDES transmitter and receiver interfaces in the same GPIO bank , use an external PLL.
- To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
- You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
- In each instance, you can use up to the following number of channels:
- 12 transmitters
- 11 DPA or non-DPA receivers, with one inclock for the I/O PLL
- 8 soft-CDR receivers
- Generate the IOPLL Intel® FPGA IP and ensure that the .qsf file lists the IOPLL IP before the LVDS SERDES IP. This order is required for your design to compile with the proper clock constraints.
- Connect the same PLL to both the transmitter and receiver instances. You can either use the tx_coreclock from the LVDS SERDES transmitter instance or the rx_coreclock from the LVDS SERDES receiver instance to clock your core logic. For the RX Soft-CDR mode, connect the tx_coreclock of the LVDS SERDES transmitter instance to the ext_coreclock port of the LVDS SERDES receiver instance.
- Set the I/O standard for the refclk port of the IOPLL IP to be compatible with the I/O standard used by the LVDS SERDES IP.
Related Information