Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 9/05/2024
Public
Document Table of Contents

6.2. LVDS SERDES Source-Synchronous Timing Budget

The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.