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1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
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3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
The F-Series and I-Series LVDS SERDES transmitters are dedicated circuitries.
Each dedicated transmitter circuitry consists of:
- A true differential buffer
- A serializer
- I/O PLLs that you can share between the SERDES transmitter and receiver
Dedicated Circuitry / Feature | Description |
---|---|
Differential I/O buffer | Supports True Differential Signaling I/O standard, which is compatible with LVDS, RSDS, and Mini-LVDS. |
SERDES | 3 to 10-bit wide serializer |
Phase-locked loops (PLLs) | Clocks the load and shift registers |
Programmable VOD | Adjusts the output voltage swing |
Programmable pre-emphasis | Boosts output current |