ID
721819
Date
9/05/2024
Public
Visible to Intel only — GUID: cjn1629100033664
Ixiasoft
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
2. Agilex™ 7 F-Series and I-Series LVDS SERDES Architecture
3. Agilex™ 7 F-Series and I-Series LVDS SERDES Transmitter
4. Agilex™ 7 F-Series and I-Series LVDS SERDES Receiver
5. Agilex™ 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: F-Series and I-Series
Visible to Intel only — GUID: cjn1629100033664
Ixiasoft
1. Agilex™ 7 F-Series and I-Series LVDS SERDES Overview
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
The Agilex™ 7 F-Series and I-Series I/O system includes three types of I/O interfaces: general purpose I/Os (GPIO), Secure Device Manager (SDM) I/O, and Hard Processor System (HPS) I/O. Each I/O interface caters to different interfacing requirements.
F-Series and I-Series devices support LVDS serializer/deserializer (SERDES) through the True Differential Signaling I/Os in the GPIO banks. The true differential I/Os are capable of supporting LVDS interfaces, including subsets such as:
- RSDS
- Mini-LVDS
- Any I/O standards using equivalent electrical specifications
F-Series and I-Series devices support SERDES on all True Differential Signaling GPIO banks with the following features:
- SERDES interfaces up to 1.6 Gbps.
- Differential 100-ohm OCT RD.
- Differential I/O reference clock for the I/O PLL that drives the SERDES.
- Dedicated transmitter and dedicated receiver differential pin pairs in each I/O bank with multiple usage modes options.
- In each I/O bank, there are 24 receiver channels with SERDES and DPA, and 24 transmitter channels with SERDES. The total number of SERDES channels varies across F-Series and I-Series devices, depending on the total number of pins available in the package.