F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

1.1. IP Core Overview

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP is the multirate version of F-Tile PMA/FEC Direct PHY Intel FPGA IP, which is meant for dynamic reconfiguration usage.
The IP provides the options to specify the startup settings, and targeted dynamic reconfiguration settings. During generation, the IP instantiates the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP for its startup and dynamic reconfiguration profiles.
Note: You can currently use the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP only along with the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. Refer to the F-Tile Dynamic Reconfiguration Design Example User Guide for quick reference on how to connect and simulate these two IPs.

The IP currently supports the following reconfiguration modes:
  • Data rate reconfiguration
  • Reference clock switching
  • PMA width reconfiguration
  • RS-FEC mode reconfiguration
  • Duplex and simplex mode reconfiguration
  • PMA Direct to FEC Direct mode reconfiguration
  • FEC to non-FEC mode reconfiguration
  • PAM4 to NRZ signaling reconfiguration
  • TX FGT PLL reconfiguration
  • RX FGT CDR reconfiguration
  • TX/RX user clock reconfiguration
The IP currently does not support the following reconfiguration modes:
  • FGT to FHT reconfiguration
  • Duplex mode to simplex mode reconfiguration
  • System PLL reconfiguration
  • Reference clock reconfiguration for system PLL

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP allows you to enable the Datapath Avalon® Memory-Mapped Interface to access the soft CSR and reconfiguration soft CSR registers and PMA Avalon® Memory-Mapped Interface to access the PMA registers.

Note: The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP currently does not support FHT reconfiguration. Support is planned in a future release of the Intel® Quartus® Prime Pro Edition software.

Section Content
Reconfiguration Group
Base Profile
Secondary Profiles
Startup Profile
Supported Reconfiguration Groups

Level Two Title