F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

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2.6. RS-FEC Signals

The following table describes the RS-FEC signals that are a part of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 13.  RS-FEC Signals
Signal Name Clocks Domain/Resets Direction Description
rsfec_status_rx_not_deskew[M-1:0] Asynchronous Output All RX lanes locked but the alignment markers were not unique or the skew was too large. Only applicable in multi-lane.
rsfec_status_rx_not_locked[M-1:0] Asynchronous Output RX lane not locked. Not locked to alignment and codeword markers or RS-FEC codewords (when not using markers). Only applicable in multi-lane.
rsfec_status_rx_not_align[M-1:0] Asynchronous Output Incoming signal fail, RX lanes not all locked, alignment markers not unique or skew too large. Only applicable in multi-lane.
rsfec_sf[M-1:0] Asynchronous Output Signal fail, low means RS-FEC is aligned(fec_ready is high and rsfec_status_not_aligned is low)
fec_snapshot[M-1:0] Asynchronous Input Takes a snap of RS-FEC status to CSR, uses Avalon® memory-mapped to read the content. To avoid a SSR variation delay between different streams in aggregate mode for RS-FEC error counters across multiple streams, stop traffic before taking the snapshot.