F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

2.2. Reset Signals

Each of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP core ports has its own set of reset signals. The bit width of the tx_reset port is same as the maximum number of fractures possible. For example, in a 100G-4 reconfigurable group, if the system starts up as 1 fracture using all 4 PMAs, then the reset for all the PMAs should come from tx_reset[0].

The following table describes the reset and reset status signals that are a part of the reset interface of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 8.  Reset and Reset Status Signals
Signal Name Clock Domain Direction Description
tx_reset[M-1:0] Asynchronous Input TX reset input for TX PMA and TX datapath. Must be asserted until tx_reset_ack is asserted.
rx_reset[M-1:0] Asynchronous Input RX reset input for RX PMA and RX datapath. Must be kept asserted until rx_reset_ack is asserted.
tx_reset_ack[M-1:0] Asynchronous Output TX reset complete indicator.
rx_reset_ack[M-1:0] Asynchronous Output RX reset complete indicator.
tx_am_gen_start[M-1:0] Asynchronous Output When using FEC mode, indicates when to start sending alignment markers. This clears once tx_am_gen_2x_ack is asserted.
tx_am_gen_2x_ack[M-1:0] Asynchronous Input When using FEC mode, indicates to the reset sequencer at least 2 alignment markers were sent since tx_am_gen_start is asserted. This signal is deasserted after tx_am_gen_start is deasserted.
tx_ready[M-1:0] Asynchronous Output Status port to indicate when TX PMA and TX datapath are reset successfully and ready for data transfer.
rx_ready[M-1:0] Asynchronous Output If RX de-skew is disabled: status port to indicate when RX PMA and RX datapath are reset successfully and ready for data transfer. If RX de-skew is enabled: status port to indicate when RX PMA and RX datapath are reset successfully, RX de-skew is done, and ready for data transfer.
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