F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

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2.2. Reset Signals

Each of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP core ports has its own set of reset signals. The bit width of the tx_reset port is same as the maximum number of fractures possible. For example, in a 100G-4 reconfigurable group, if the system starts up as 1 fracture using all 4 PMAs, then the reset for all the PMAs should come from tx_reset[0].

The following table describes the reset and reset status signals that are a part of the reset interface of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 8.  Reset and Reset Status Signals
Signal Name Clock Domain Direction Description
tx_reset[M-1:0] Asynchronous Input TX reset input for TX PMA and TX datapath. Must be asserted until tx_reset_ack is asserted.
rx_reset[M-1:0] Asynchronous Input RX reset input for RX PMA and RX datapath. Must be kept asserted until rx_reset_ack is asserted.
tx_reset_ack[M-1:0] Asynchronous Output TX reset complete indicator.
rx_reset_ack[M-1:0] Asynchronous Output RX reset complete indicator.
tx_am_gen_start[M-1:0] Asynchronous Output When using FEC mode, indicates when to start sending alignment markers. This clears once tx_am_gen_2x_ack is asserted.
tx_am_gen_2x_ack[M-1:0] Asynchronous Input When using FEC mode, indicates to the reset sequencer at least 2 alignment markers were sent since tx_am_gen_start is asserted. This signal is deasserted after tx_am_gen_start is deasserted.
tx_ready[M-1:0] Asynchronous Output Status port to indicate when TX PMA and TX datapath are reset successfully and ready for data transfer.
rx_ready[M-1:0] Asynchronous Output If RX de-skew is disabled: status port to indicate when RX PMA and RX datapath are reset successfully and ready for data transfer. If RX de-skew is enabled: status port to indicate when RX PMA and RX datapath are reset successfully, RX de-skew is done, and ready for data transfer.