F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

2. Interface Overview

This section describes various interfaces of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP core.
The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP has the following interfaces:
  • Clock signals
  • Reset signals
  • TX and RX serial and parallel data signals
  • Custom Cadence control and status signals
  • TX and RX PMA status signals
  • RS-FEC signals
  • TX and RX PMA FIFO signals
  • PMA Avalon® memory-mapped interface signals
  • Datapath Avalon® memory-mapped interface signals
Some of the interfaces of the IP are fracture based. The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP provides mapping for such interfaces from LSB to MSB. The mapping is used for all the reconfiguration groups.
Note: Some ports are only available in the Profile #0 tab.
Table 6.  Variables Defining Bits for the Interfacing Ports in Port and Signal Reference
Variable Values Description
<N>

FGT: 1, 2, 4, 6, 8, 12, 16

N is the number of PMA lanes.
<n> 0 to N-1 n is the PMA index number.
<X>

PMA width = 8, 10, 16, 20, and 32-bit, X=1

PMA width = 64-bit, X=2

PMA width = 128-bit, X=4

X is the number of streams.
<x> 0 to X-1 x is the stream index.
<M> 1 to 12 Maximum number of fracture groups.
<m> 0 to 11 Index of fracture groups.
<J> 0 to 32 Number of profiles.
<j> 0 to 32 Index of profiles.

Section Content
Clock Signals
Reset Signals
TX and RX Parallel and Serial Signals
Custom Cadence Control and Status Signals
TX and RX PMA Status Signals
RS-FEC Signals
TX and RX PMA FIFO Signals
PMA Avalon Memory-Mapped Signals
Datapath Avalon Memory-Mapped Signals

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