F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

3.1. Dynamic Reconfiguration QSF Settings

This section describes the QSF settings required for dynamic reconfiguration to work for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

General QSF Settings

The following table describes the general QSF setting that is required and its use.
Table 23.  Dynamic Reconfiguration QSF Setting for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP
QSF Settings Description
set_instance_assignment -name IP_COLOCATE F_TILE -from <hpath1> -to <hpath2> -entity <top_level_name>

Associates a Dynamic Reconfiguration Controller with the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP that it is controlling.

The <hpath1> is the hierarchy path of the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP in your design and <hpath2> is the hierarchy path of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP in your design.

set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL -to <bb_instance_hpath> <clock-port-name>

When you have more than one F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP instance and the instance has the Reconfiguration Clock Source parameter set to external, assign the reconfiguration clock source with this .qsf assignment. This step assigns the master clock for the indicated protocol PHY IPs.

If your design is duplex or TX simplex mode, use the following clock source for the <clock-port-name>: pld_pcs_tx_clk_out1_dcm. If your design is RX simplex mode, use the following clock source for the <clock-port-name>: pld_pcs_rx_clk_out1_dcm

Note: Refer to the Reconfiguration Clock Source parameter description in Parameter Settings: General Tab table for more information.
The following example .qsf assignment illustrates the setting for a design using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP: 
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 \
-to dut|directphy_f_dr_0
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