F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

5. Block Description

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP enables you to use all the features and components of the F-Tile to get more bandwidth than what is available in the existing single rate F-Tile PMA/FEC Direct PHY Intel FPGA IP.
The following block diagram shows the interconnections of F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP. It consists of a soft IP (SIP) and hard IP (HIP) module that are used for startup, and profile instances.
Figure 18. Block Diagram

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP includes a soft IP (SIP) that enables a customer to use all the features and components of the F-tile transceiver hard IP (HIP) to get more bandwidth than what is available in the existing single rate F-Tile PMA/FEC Direct PHY Intel FPGA IP.

The F-tile is connected to the FPGA fabric using embedded multi-die interconnect bridge (EMIB) technology. The EMIB Deskew block corrects for possible skew over the EMIB interfaces between the main FPGA die and the F-Tile.

The PMA can be of FGT type. The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP gets its clock from the system PLL. Internally generated clocks are used to drive the data. The default base profile represents the maximum resources available in the generated IP. It is labeled Profile #0 in the GUI.

The IP receives its main clock input from the F-Tile Reference and System PLL Clocks Intel FPGA IP. The system PLL frequency must be at least twice the frequency of the rate at which parallel data is driven or received. The default system PLL frequency in the IP is 830.078125 MHz and the reference clock frequency for the TX PLL lock and RX CDR is 156.25 MHz.

The soft IP module (SIP) is the control logic for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP. It includes glue logic that multiplexes signals to the correct PMA lane. For example, a 1-bit tx_reset signal can directly go to the corresponding transmitter. The bit width of tx_reset port is equal to the maximum number of fractures possible. For example, in a 100G-4 Reconfigurable group, if the system starts up as one fracture using all four PMA lanes, then the reset for all lanes should come from tx_reset[0].

The purpose of the custom cadence logic is to allow you to pace tx data valid with tx_cadence signal in case there is a possibility of FIFO overflow. The functionality is same as the single rate F-Tile PMA/FEC Direct PHY Intel FPGA IP core.

The deskew logic includes TX deskew pulse insertion in the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP. The logic is used to align the lanes belonging to the same transmitter together at the receiver for PMA direct mode. For FEC direct mode, the logic aligns lanes belonging to the same fracture and subsystem.

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