F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

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3.2. QSF settings for Different Reconfiguration Profiles

In addition to the general QSF setting, there are applications where one of the PMA lanes may need to reconfigure to lower data rates which would require bypassing the RX auto adaptation. The FGT PMA uses automatic RX adaptation, unless you add QSF assignments in the .qsf file.

You need to add QSF settings based on the profile information to bypass the RX adaptation for the PMA lanes. To add the QSF settings, you have to get the <top_level_instantiation_name> and the profile information from the <top>.tlg.rpt file by searching for BB_F_UX_TX and BB_F_UX_RX instantiations and profile names for the TX and RX respectively.

The <top>.tlg.rpt file has the path in the following format:
  • <top_level_instantiation_name> : F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP top level instantiation name.
  • <x> : secondary profile number starts from 1 (up to the maximum profiles configured).
  • <n> : in perxcvr[n], n is the PMA lane count. Use 0 for a single PMA lane configuration. For profiles configuring multiple PMA lanes, this is 1..<n-1> up to the maximum PMA lane count set in that profile with same Profile Group ID.
An example of the <top>.tlg.rpt file with a search for BB_F_UX_TX instance is shown below:
; -- BB_F_UX_TX ; dut|directphy_f_dr_0|U_sec_profile2|sec_profile_2|dphy_hip_inst|persystem[0].perxcvr[2].fgt.tx_ux.x_bb_f_ux_tx ; 
In the example above, the BB_F_UX_TX instance from the <top>.tlg.rpt file contains the reconfiguration profile settings of:
  • <top_level_instantiation_name> : dut
  • <x> : secondary profile = 2
  • <n> : PMA lane count number = 3, in perxcvr[2]