F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

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4.2.1. Reference and System PLL Clock for your IP Design

You must instantiate one F-Tile Reference and System PLL Clocks Intel FPGA IP if you are configuring your design with the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP performs these main functions:
  1. Configure reference clock for FGT PMA:
    • Enable FGT reference clocks and specify the reference clock frequency
    • Specify FGT CDR output
  2. Configure system PLL:
    • Enable system PLL and specify its mode
    • Specify the reference clock source and frequency for system PLL

    When using the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP, you can only clock the PMA direct and FEC direct modes with system PLL clocking mode. PMA clocking mode is not supported for dynamic reconfiguration process. The System PLL output frequency defaults to 830.078125 MHz.

    The Sys PLL clock Div2 is used to clock the soft IP (SIP) module of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP. For example, it drives the coreclkin ports of this IP.

Note: In your IP design, you must include an F-Tile Reference and System PLL Clocks Intel FPGA IP core to pass logic generation flow.

The F-Tile Reference and System PLL Clocks Intel FPGA IP must always connect to a protocol based Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP cannot be compiled or simulated as a standalone IP. For more information on parameters and port list for F-Tile Reference and System PLL Clocks Intel FPGA IP core, refer to the F-tile Architecture and PMA/FEC Direct PHY IP User Guide.

When you design multiple interfaces or protocol-based IP cores within a single F-tile, you must use only one instance of the F-Tile Reference and System PLL Clocks Intel FPGA IP core to configure:
  • All required reference clocks for FGT PMA (up to 10) and FHT PMA (up to 2) to implement multiple interfaces within a single F-tile.
  • All required System PLLs (up to 3) to implement multiple interfaces within a single F-tile.
  • All required reference clocks for system PLLs (up to 8 – shared with FGT PMA) to implement multiple interfaces within a single F-tile.