F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP parameter settings are similar to the single rate F-Tile PMA/FEC Direct PHY Intel FPGA IP except some parameters and ports are not applicable and hence not visible in the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP GUI.

The F-Tile PMA/FEC Direct Multirate PHY Intel FPGA IP has additional parameters such as Reconfiguration group, Reconfiguration subset, Number of secondary profiles, Target fracture, Profile group id and Use profile for startup for setting up the reconfiguration profiles.

The secondary profile must use all of the PMA lanes allocated for the reconfiguration group, either within a single profile or in multiple profiles by using the same Profile group id. The same parameter settings selected for Profile #N IP Configuration can be reused within the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP with different Common Datapath Options PN (N=0-32), TX Datapath Options PN (N=0-32), RX Datapath Options PN (N=0-32) or RS-FEC PN (N=0-32) settings.

You can have Profile #1 with RS-FEC disabled, using the Profile #1 IP Configuration settings for Profile #1 as;
  • Reconfiguration subset = 50G-1
  • Target fracture = 0
  • Profile group id = 1
  • Enable RS-FEC use = On
  • Enable RS-FEC = Off
You can configure Profile #2 with the same Profile #2 IP Configuration settings with RS-FEC enabled;
  • Reconfiguration subset = 50G-1
  • Target fracture = 0
  • Profile group id = 1
  • Enable RS-FEC use = On
  • Enable RS-FEC = On

Section Content
Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core

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