F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

2.5. TX and RX PMA Status Signals

The following table describes the TX and RX PMA status signals that are a part of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 11.  TX PMA Status SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
fgt_tx_beacon[N-1:0] Asynchronous Input

1'b1: enable SATA beacon signal.

1'b0: disable SATA beacon signal.

tx_pll_locked[N-1:0] Asynchronous Output TX channel PLL locked signal for both FGT and FHT to reference clock within the PPM threshold status signal for fast/medium or slow PLL. 1’b1 = locked. 1’b0 = not locked.
Table 12.  RX PMA Status Signals
Signal Name Clocks Domain/Resets Direction Description
fgt_rx_signal_detect[N-1:0] Asynchronous Output FGT RX signal detect indicator.
fgt_rx_signal_detect_lfps[N-1:0] Asynchronous Output

Indicates SATA low frequency periodic signaling (LFPS) signal detection.

rx_is_lockedtoref[N-1:0] Asynchronous Output CDR lock status signal.
  • 1’b1 – CDR is frequency locked to reference clock within the PPM threshold.
  • 1’b0 – CDR is not frequency locked within the PPM threshold. Applicable to FGT PMA only

When lockedtodata stays high, the lockedtoref signal status is insignificant.

rx_is_lockedtodata[N-1:0] Asynchronous Output RX CDR data lock status signal.
  • 1’b0: CDR is not locked to data.
  • 1’b1: CDR is locked to data. Applicable to both FGT and FHT PMA.

When asserted, indicates that the CDR is in locked-to-data mode. When continuously asserted and does not switch between asserted and deasserted, you can confirm that the CDR is actually locked to data.

fgt_rx_set_locktoref[N-1:0] Asynchronous Input

1'b1: keep CDR in lock to reference mode.

1'b0: keep CDR in auto mode.

fgt_rx_cdr_freeze[N-1: 0] Asynchronous Input This port is used in GPON to freeze the CDR lock state during inactive time-slots.
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