F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 12/19/2022
Public

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2.9. Datapath Avalon Memory-Mapped Signals

The following table describes the Datapath Avalon® memory-mapped signals that are a part of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 16.  Datapath Avalon® Memory-Mapped Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_pdp_clk N/A Input Reconfig Interface Clock
reconfig_pdp_reset reconfig_pdp_clk Input Parallel data path reconfiguration interface reset. This reset must be asserted at least once after power on.
reconfig_pdp_address[13+K d :0] reconfig_pdp_clk Input Reconfig Interface Address. K d=Ceiling(log2(N)). Word address. EMIB core adapter and soft CSR registers use unused space of F-tile Datapath Avalon® memory mapped 16-bit address.
reconfig_pdp_byteenable[3:0] reconfig_pdp_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, 32-bit Dword Access is assumed; otherwise byte access is used.
reconfig_pdp_write reconfig_pdp_clk Input Reconfig Write
reconfig_pdp_read reconfig_pdp_clk Input Reconfig Read
reconfig_pdp_writedata[31:0] reconfig_pdp_clk Input Reconfig Write data
reconfig_pdp_readdata[31:0] reconfig_pdp_clk Output Reconfig Read data
reconfig_pdp_waitrequest reconfig_pdp_clk Output Reconfig Wait Request
reconfig_pdp_readdatavalid reconfig_pdp_clk Output Reconfig Read Data Valid. Optional port, available if the port is enabled in parameter editor.