F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

Download PDF
ID 720998
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

3.2.1. Bypass RX Adaptation QSF Settings

The .qsf assignments to bypass the RX adaptation are: 
set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to \
<top_level_instantiation_name>|directphy_f_dr_0|U_sec_profile<x>|sec_profile_<x>|dphy_hip_inst|persystem[0].per xcvr[n].fgt.rx_ux.x_bb_f_ux_rx \
-entity <top_level_name>

set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to \
<top_level_instantiation_name>|directphy_f_dr_0|U_sec_profile<x>|sec_profile_<x>|dphy_hip_inst|persystem[0].per xcvr[n].fgt.tx_ux.x_bb_f_ux_tx \
-entity <top_level_name>

set_instance_assignment -name HSSI_PARAMETER "rx_adapt_mode=RX_ADAPT_MODE_STATIC_EQ" -to \
<top_level_instantiation_name>|directphy_f_dr_0|U_sec_profile<x>|sec_profile_<x>|dphy_hip_inst|persystem[0].per xcvr[n].fgt.rx_ux.x_bb_f_ux_rx \
-entity <top_level_name>

set_instance_assignment -name HSSI_PARAMETER "engineered_link_mode=ENABLE" \
-to <top_level_instantiation_name>|directphy_f_dr_0|U_sec_profile<x>|sec_profile_<x>|dphy_hip_inst|persystem[0].per xcvr[n].fgt.tx_ux.x_bb_f_ux_tx \
-entity <top_level_name>

set_instance_assignment -name HSSI_PARAMETER "engineered_link_mode=ENABLE" -to <top_level_instantiation_name>|directphy_f_dr_0|U_sec_profile<x>|sec_profile_<x>|dphy_hip_inst|persystem[0].perx cvr[n].fgt.rx_ux.x_bb_f_ux_rx \
-entity <top_level_name>

For example, with top level instantiation name of u0 and secondary profile 2 (x=2) and one PMA lane count (n=0), the .qsf assignment is shown below: 

set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" \
-to u0|directphy_f_dr_0|U_sec_profile2|sec_profile_2|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx \
-entity top

Similarly for the base profile (profile #0), an example .qsf assignment is shown below: 

set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" \
-to u0|directphy_f_dr_0|U_base_profile|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx \
-entity top
Level Two Title