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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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2. Quick Start Guide
The Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP for Agilex™ 7 (F-Tile) devices provides the capability of generating design examples for selected configurations.
Figure 1. Development Stages for the Design Example