Visible to Intel only — GUID: nfa1462536131043
Ixiasoft
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
Visible to Intel only — GUID: nfa1462536131043
Ixiasoft
3.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-low . Asserting this signal resets all channels and their components. Upon power-up, reset the design example (i_rst_n, i_tx_rst_n, and i_rx_rst_n).
Figure 10. Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With and Without IEEE 1588v2 Feature (Reset is common for all instance)
For more details on the reset signals, refer to Clock and Reset Interface Signals.