F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3.5. Hardware Testing

Follow the procedure in Compiling and Testing the Design in Hardware to test the design example in the selected hardware.

In the Clock Controller application, which is part of the development kit, ensure the frequencies are set as follows:

  • Si5332, OUT6—125 MHz (clk_125)
  • ZL30733, OUT3—156.25 MHz (refclk_10g)