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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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3.5. Hardware Testing
Follow the procedure in Compiling and Testing the Design in Hardware to test the design example in the selected hardware.
In the Clock Controller application, which is part of the development kit, ensure the frequencies are set as follows:
- Si5332, OUT6—125 MHz (clk_125)
- ZL30733, OUT3—156.25 MHz (refclk_10g)
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