2.5.1. Signal Tap Debug Signals
Signal | Description |
---|---|
avalon_st_tx_valid | Assert this signal to indicate that the avalon_st_tx_data signal and other signals on this interface are valid. |
avalon_st_tx_ready | When asserted, indicates that the MAC IP is ready to accept data. The reset value of this signal is nondeterministic. |
avalon_st_tx_startofpacket | Assert this signal to indicate the beginning of the TX data. |
avalon_st_tx_endofpacket | Assert this signal to indicate the end of the TX data. |
avalon_st_tx_data[63:0] | TX data from the client. |
avalon_st_tx_empty[2:0] | Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data. |
avalon_st_tx_error | Assert this signal to indicate that the current TX packet contains errors. |
avalon_st_rx_valid | Assert this signal to indicate that the avalon_st_rx_data signal and other signals on this interface are valid. |
avalon_st_rx_ready | Assert this signal when the client is ready to accept data. |
avalon_st_rx_startofpacket | When asserted, indicates the beginning of the RX data. |
avalon_st_rx_endofpacket | When asserted, indicates the end of the RX data. |
avalon_st_rx_data[63:0] | RX data to the client. |
avalon_st_rx_empty[2:0] | Contains the number of empty bytes during the cycle that contain the end of the RX data. |
avalon_st_rx_error[5:0] | When set to 1, the respective bits indicate an error type:
|
avalon_st_txstatus_valid | When asserted, this signal qualifies the avalon_st_txstatus_data and avalon_st_txstatus_error signals. |
avalon_st_rx_valid | When asserted, indicates that the avalon_st_rx_data signal and other signals on this interface are valid. |
avalon_st_txstatus_data[39:0] | Contains information about the TX frame.
|
avalon_st_txstatus_error[6:0] | When set to 1, the respective bit indicates the following error type in the TX frame:
|
avalon_st_rxstatus_valid | When asserted, this signal qualifies the avalon_st_rxstatus_data and avalon_st_rxstatus_error signals. The MAC IP asserts this signal in the same clock cycle the avalon_st_rx_ endofpacket signal is asserted. |
avalon_st_rxstatus_data[39:0] | Contains information about the RX frame.
|
avalon_st_rxstatus_error[6:0] | When set to 1, the respective bit indicates the following error type in the RX frame.
The error status is invalid when an overflow occurs. |
led_an | Asserted when auto-negotiation is completed. |
o_rx_pcs_ready | Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when i_rx_rst_n/i_rst_n signal asserts. |
o_cdr_lock | This signal indicates that the recovered clocks are locked to data. |
channel_tx_ready | Asserted when the channel is ready for data transmission. |
channel_rx_ready | Asserted when the channel is ready for data transmission. |
rx_block_lock | Asserted when the link synchronization is successful. |
frame_dropped | Frame dropped signal from the RX block. |
overflow_reg | Overflow bit from the RX block. |
eop_extended | Extended end of packet signal from the RX block. |
rx_rs2fctl_frm_error | Frame error bit signal in the RX block. |
rx_rs2fctl_frm_data [31:0] | Frame input data signal . |
rx_rs2fctl_frm_sop | Start of packet input signal at RX block frame. |
rx_rs2fctl_frm_eop | End of packet input signal at RX block frame. |
rx_rs2fctl_frm_valid | Input valid signal at RX block frame. |
rx_rs2fctl_frm_empty [1:0] | Input empty signal at RX block frame. |
rx_fltrpcrem2pa_frm_data [31:0] | Frame output data. |
rx_fltrpcrem2pa_frm_sop | Start of packet output signal at RX block frame. |
rx_fltrpcrem2pa_frm_eop | End of packet output signal at RX block frame. |
rx_fltrpcrem2pa_frm_valid | Output valid signal at RX block frame. |
rx_fltrpcrem2pa_frm_empty [1:0] | Output empty signal at RX block frame. |
rx_fltrpcrem2pa_frm_error | Frame error bit in the RX block. |
Note: The signal tap debug signals are targetted for channel 0 and are used in channel 0 tests.