F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3.3.3.1.3. Run-time Reset Sequence—TX + RX

Figure 13. Reset Sequence
The following steps describe IP core reset sequence as shown in the waveform.
  1. Drive the i_rst_n reset signal high while i_tx_rst_n and i_rx_rst_n reset signals are already deasserted.
  2. The o_rst_ack_n reset signal deasserts. This indicates that the IP core is no longer in the full reset.
    Note: This step doesn't indicate that the IP core is in fully functional state.
    Note: The o_tx_rst_ack_n and o_rx_rst_ack_n reset signals also deassert. The exact sequence and timing is not guaranteed.
  3. The IP core is fully out of reset. Assert o_tx_lanes_stable and o_rx_pcs_ready to indicate that the TX and RX datapaths are ready for use.
  4. Assert the i_tx_rst_n reset signal.
  5. The o_tx_lanes_stable signal deasserts to indicate that the TX datapath is no longer operational.
  6. The o_tx_rst_ack_n signal asserts indicating that the TX datapath is fully in reset. Then, deassert the i_tx_rst_n signal to bring the TX datapath out of the reset.
  7. Assert the i_rx_rst_n reset signal.
  8. The o_rx_pcs_ready signal deasserts to indicate that the RX datapath is no longer operational.
  9. The o_rx_rst_ack_n signal asserts indicating that the RX datapath is fully in reset. Then, deassert the i_rx_rst_n signal to bring the RX datapath out of the reset.
  10. Assert the i_rst_n reset signal.
  11. The o_tx_lanes_stable and o_rx_pcs_ready signals deassert to indicate that TX and RX datapath are no longer operational.
  12. The o_rst_ack_n signals assert to indicate the IP core is fully in reset. To bring the IP core out of the reset, deassert the i_rst_n reset signal.