Visible to Intel only — GUID: tii1486968980123
Ixiasoft
Visible to Intel only — GUID: tii1486968980123
Ixiasoft
4.1. Clock and Reset Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
csr_clk | In | 1 | 125 MHz configuration clock for the Avalon® memory-mapped interface and core logic. |
i_reconfig_reset | In | 1 | Active-high reset signal for the Avalon® memory-mapped interface. |
i_tx_rst_n | In | 1 | Active-low reset asynchronous signal. Resets the entire TX datapath, including the TX PCS, TX MAC, and TX PMA. Do not deassert until the o_rst_ack_n asserts. |
i_rx_rst_n | In | 1 | Active-low reset asynchronous signal. Resets the entire RX datapath, including the RX PCS, RX MAC, and RX PMA. Do not deassert until the o_rst_ack_n asserts. |
mac64b_clk mac32b_clk |
Out | 1 | 156.25 MHz and 312.5 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk. |
refclk_10g | In | 1 | 156.25 MHz reference clock for the System PLL. |
reset | In | 1 | Assert this asynchronous and active-high signal to reset the whole design example. |
tx_digitalreset | Out | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY. |
rx_digitalreset | Out | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY. |
i_rst_n | In | 1 | Active-low reset asynchronous signal. Do not deassert until the o_rst_ack_n signal is asserted ('0'). Resets the TX interface (TX PCS and TX MAC), RX interface (RX PCS and RX MAC), TX PMA, and RX PMA. This reset leads to the assertion of the o_rst_ack_n output signal. |