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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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2.3.1. Procedure
You can compile and simulate the design by running a simulation script from the command prompt.
- Navigate to the LL10G_10G_USXGMII folder in your design example: cd <your_design_path>/LL10G_10G_USXGMII.
Note: For designs with IEEE 1588v2 enabled, navigate to LL10G_10G_USXGMII_1588v2 folder: cd <your_design_path>/LL10G_10G_USXGMII_1588v2.
- Run the following command: quartus_tlg altera_eth_top.
- Copy the altera_eth_top_*_.mif file to the following directory: cp <your_design_path>/LL10G_10G_USXGMII/support_logic/altera_eth_top__*_*.mif simulation/ed_sim/setup_scripts/.
- Navigate to the sim directory: cd simulation/ed_sim/setup_sripts/.
- Run the following command: ip-setup-simulation -quartus-project=../../../altera_eth_top.qpf
- At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .
- Run the following simulation scripts.
Simulator Working Directory Command ModelSim* <Example Design>/simulation/ed_sim/mentor vsim -do altera_tb_run.tcl VCS* <Example Design>/simulation/ed_sim/synopsys/vcs sh altera_tb_run.sh Xcelium* <Example Design>/simulation/ed_sim/xcelium sh altera_tb_run.sh
A successful simulation ends with the following message:
Simulation passed.
After successful completion, you can analyze the results.