F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

2.3.1. Procedure

You can compile and simulate the design by running a simulation script from the command prompt.
  1. Navigate to the LL10G_10G_USXGMII folder in your design example: cd <your_design_path>/LL10G_10G_USXGMII.
    Note: For designs with IEEE 1588v2 enabled, navigate to LL10G_10G_USXGMII_1588v2 folder: cd <your_design_path>/LL10G_10G_USXGMII_1588v2.
  2. Run the following command: quartus_tlg altera_eth_top.
  3. Copy the altera_eth_top_*_.mif file to the following directory: cp <your_design_path>/LL10G_10G_USXGMII/support_logic/altera_eth_top__*_*.mif simulation/ed_sim/setup_scripts/.
  4. Navigate to the sim directory: cd simulation/ed_sim/setup_sripts/.
  5. Run the following command: ip-setup-simulation -quartus-project=../../../altera_eth_top.qpf
  6. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .
  7. Run the following simulation scripts.
    Simulator Working Directory Command
    ModelSim* <Example Design>/simulation/ed_sim/mentor vsim -do altera_tb_run.tcl
    VCS* <Example Design>/simulation/ed_sim/synopsys/vcs sh altera_tb_run.sh
    Xcelium* <Example Design>/simulation/ed_sim/xcelium sh altera_tb_run.sh
A successful simulation ends with the following message:
Simulation passed.
After successful completion, you can analyze the results.