F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3.3.2. Clocking Scheme

Figure 8. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example Without IEEE 1588v2 Feature
Figure 9. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature