F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

The 10M/100M/1G/2.5G/5G/10G (USXGMII) design example demonstrates an Ethernet solution for Agilex™ 7 (F-Tile) devices using the Low Latency Ethernet 10G MAC Intel® FPGA IP operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.

Generate the design example from the Example Design tab of the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor. You can choose to generate the design example with or without the IEEE 1588v2 feature.