F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3.3.1. Design Components

Table 7.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Use legacy Avalon Memory-Mapped Interface: Not selected
  • Use legacy Avalon Streaming Interface: Selected
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Enable asymmetry support: Not selected
  • Enable peer-to-peer support: Not selected
  • Timestamp fingerprint width: 4
  • Time Of Day format: Enable both 96b and 64b time-of-day format
PHY The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Speed: 10M/100M/1G/2.5G/5G/10G
  • Enabled IEEE 1588 Precision Time Protocol: Selected
  • Connect to NBASE-T PHY: Selected
  • Reference clock frequency for 10GbE (MHz): 156.250000
Channel address decoder Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC.
Multi-channel address decoder Decodes the addresses of the components used by all channels.
Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.
SYS PLL

F-Tile Reference and System PLL Clocks Intel® FPGA IP that generates reference clock and system PLL clocks for the Agilex™ 7 Transceiver.

Design Components for the IEEE 1588v2 Feature
Master TOD The master TOD for all channels.
TOD Synch Synchronizes the master TOD to all local TODs.
Local TOD The TOD for each channel.
TX Packet Classifier Classify transmitting packet and generate corresponding PTP packet command to the MAC IP.
Deterministic Latency Sampling PLL Generates sampling clock for latency measurement.
TOD Sync Sampling PLL Generates sampling clock for TOD Synchronizer.
Pulse Per Second Generates pulse per second (pps) based on TOD.