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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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2.5. Signal Tap Debugging
The IP provides a list of predefined debug signals to capture the behavior of the design example components.
To program the hardware design example on Agilex™ 7 devices:
- Click Tools > Signal Tap Logic Analyzer.
- Click Hardware Setup and select respective hardware for programming.
- Click on Scan Chain to select the proper JTAG.
- Click on the SOF Manager to browse and program the SOF.
- After the programming is complete, click any of the signals under the Setup window to view the signal behavior.
- In the Instance Manager toolbar, click Run Analysis. The signal capture and signal transitions is displayed in the Data window.
- Refer to the Signal Tap Logic Analyzer Introduction for more information about Signal Tap.
To start the signal tap debugging:
- Generate the design example for the Low Latency Ethernet 10G MAC IP.
- Open the .qpf file in the intel_eth_em10g32_0_EXAMPLE_DESIGN/LL10G_10G_USXGMII/ directory.
- In the Quartus® Prime Pro Edition software, click File > Open > <LL10G_10G_USXGMII*> > *.stp