F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3.5.2. Design Constraints

The following is the current constraint statements in the project .qsf file:
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
You must replace the constraint statements in the project .qsf file if you are using the following version of the Agilex™ 7 I-Series Transceiver SoC development kit:
Table 9.  Required Design Constraint Statements in the Project .qsf
Serial Number ID Constraint Statements Required in the Project .qsf Action Required
2000001
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
Replace the current constraints in the QSF file with these constraints.

Refer to Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide for more information on the Agilex™ 7 I-Series Transceiver-SoC development kit and their respective serial number identifier.