F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

4.2. Avalon® Memory-Mapped Interface Signals

Table 12.   Avalon® Memory-Mapped Interface Signals
Signal Direction Description

csr_mch_write

In Assert this signal to request a write to Avalon® memory-mapped address decoder.

csr_mch_read

In Assert this signal to request a read to Avalon® memory-mapped address decoder.
csr_mch_address In Use this bus to specify the register address you want to read from or write to.

csr_mch_writedata

In Carries the data to be written to the specified register.

csr_mch_readdata

Out Carries the data read from the specified register.

csr_mch_waitrequest

Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.