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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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4.2. Avalon® Memory-Mapped Interface Signals
Signal | Direction | Description |
---|---|---|
csr_mch_write |
In | Assert this signal to request a write to Avalon® memory-mapped address decoder. |
csr_mch_read |
In | Assert this signal to request a read to Avalon® memory-mapped address decoder. |
csr_mch_address | In | Use this bus to specify the register address you want to read from or write to. |
csr_mch_writedata |
In | Carries the data to be written to the specified register. |
csr_mch_readdata |
Out | Carries the data read from the specified register. |
csr_mch_waitrequest |
Out | When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests. |